Nuwan Jaliyagoda

Pera SAP-I

Simple As Possible Computer

Digital Design University Project Digital Logic Design
Pera SAP-I

This is an 8-bit Minimum Computer (AKA Simple As Possible Computer - SAP) made from simple logic ICs, flip-flops, and a few memory modules. It has a memory of 16 bytes and the maximum clock speed is not more than 5 Hz.

The whole design is based on SAP-I Architecture and the design was obtained from Ben Eater’s YouTube Channel.

Currently, this has 9 instructions (based on Intel 8080 instructions) and can be programmed using machine language (That means programming from 1s and 0s)

All the Printed Circuit boards were designed from the basics by us using Fritzing, fabricated by using the CNC, Builder_V3, soldered and assembled by us. It took 2 months to complete the fabrications and another month to build the motherboard (30x40cm) and complete the debugging.

Team

Nuwan Jaliyagoda

Nuwan Jaliyagoda

Suneth Samarasinghe

Suneth Samarasinghe

Pubudu Premathilake

Pubudu Premathilake

Dilshani Karunarathne

Dilshani Karunarathne

Wishma Herath

Wishma Herath

Pasan Thennakoon

Pasan Thennakoon

Irfan Mohammad

Irfan Mohammad