Pera SAP-I

Pera SAP-I is an 8-bit minimal computer, a Simple As Possible (SAP) machine built entirely from discrete logic ICs, flip-flops, and a few memory modules, with no microprocessor involved. It has 16 bytes of memory and a maximum clock speed of about 5 Hz, slow enough to watch data move through the machine one step at a time.

The design follows the classic SAP-I architecture and was inspired by Ben Eater’s well-known 8-bit breadboard computer series on YouTube. The computer currently supports 9 instructions, modeled on the Intel 8080 instruction set, and is programmed directly in machine language, entering programs literally as 1s and 0s.

Every circuit was first prototyped and verified on breadboards before the printed circuit boards were designed from scratch using Fritzing. The PCBs were then fabricated in-house on my CNC router, Builder V3, and soldered and assembled by our team. The fabrication took around two months, followed by another month to build the 30 x 40 cm motherboard and complete the debugging.

A detailed write-up of the project is available on my blog, a video demonstration is on YouTube, and the design files are published on GitHub.